The present invention relates to oscillators, and, more particularly, to an oscillator having an improved capacitor discharge circuit.
Conventional oscillator circuits provide clock and other timing signals as a frequency reference in electronic circuitry such as pulse width modulation (PWM) power converters, microprocessors, microcontrollers, flip-flop circuits, latch circuits, etc. A digital system may include one or more microprocessors, bus controllers, peripheral controllers, memory, and peripherals, such as disk drives, all of which may typically be synchronized from one system clock such as a precision clock signal generated by an oscillator. Precision clock signals are widely used in digital circuits to synchronize the activities of all circuits in the system, whether the system is simple or complex.
Typical oscillator circuits include a control circuit coupled to a switch-capacitor network, such that the control circuit alternately charges or discharges the voltage across the capacitor to generate an oscillatory signal appearing across the capacitor. The frequency of oscillation is determined by the rise and fall time of the charging and discharging of the capacitor.
One approach, as shown in FIG. 1, includes a set/reset (SR) flip-flop 110 and first and second comparators, 106 and 108. The interconnection between the capacitor 116 is coupled to one input of each of the comparators, 106 and 108. The other input of the first comparator 106 is coupled to receive a high threshold voltage VtH, while the other input of the second comparator 108 is coupled to receive a low threshold voltage VtL. The output of the first comparator 106 is coupled to the set input of the flip-flop 110, while the output of the second comparator 108 is coupled to the reset input of the flip-flop 110. An output of the flip-flop 110 is coupled to a first switch 112 that is coupled between capacitor 116 and a high current supply 102, where the high current supply 102 couples between the power supply rail and the first switch 112. The inverted output of the flip-flop 110 is coupled to a second switch 114 that is coupled between a low current supply 104 and ground, where the low current supply 104 couples between capacitor 116 and the second switch 114.
In operation, the first comparator 106 sets flip-flop 110, which commences the discharging of the voltage across capacitor 116, when the stored charge of capacitor 116 exceeds the predetermined high threshold voltage VtH, and the second comparator 108 resets flip-flop 110, which commences the charging of the voltage across capacitor 116, when the stored charge of capacitor 116 falls below the predetermined low threshold voltage VtL. In this manner, the signal appearing across capacitor 116 approximately oscillates between the high and the low threshold voltages, VtH and VtL, at a frequency determined by the value of capacitor 116 of the switch-capacitor network.
At times, this configuration, however, provides an unreliable oscillatory signal in that when flip-flop 110 is set in response to the switching of comparator 106, the oscillatory signal may have actually risen above the high threshold voltage VtH due to a delay in the first comparator 106. In the alternative, when flip-flop 110 is reset in response to the switching of comparator 108, the oscillatory signal may have actually fallen below the low threshold voltage VtL due to a delay in the second comparator 108. As a result, variations in the frequency of oscillation occur because the oscillatory signal does not accurately oscillate between the desired high and low threshold voltages, VtH and VtL. In most digital systems, where accuracy is a requirement, this type of error is unacceptable.
Specifically, in a PWM power converter application, the oscillator sets the operating frequency of the switching converter in the PWM power converter. In this particular application, the oscillator typically has a slow rising waveform on the capacitor 116 and a fast falling waveform on the same capacitor 116 such that the on-time for the PWM converter is longer than the off-time, where the on-time is set by the time for capacitor 116 to charge with the small current from current supply 102 and the off-time is set by the time to discharge capacitor 116 using a large current from current supply 104.
In this application, a slight delay in the first comparator 106 may not cause problems; however, a slight delay in the second comparator 108 can result in substantial undershoot and poor control of the off-time of the PWM converter. The high current of current source 104 used to discharge capacitor 116 requires comparator 108 respond immediately to the voltage of capacitor 116 and turn off the discharge cycle by resetting flip-flop 110. As such, the efficiency of oscillator 100 relies heavily upon whether comparator 108 is fast and has an accurate threshold and whether no time delays exist in the feedback loop which turns off the discharge cycle.
Known approaches, in an effort to solve the inaccuracy in the oscillatory signal, place effort into increasing the efficiency of the second current source 104 or place effort into designing a faster flip-flop 110 or a faster comparator 108. Moreover, other approaches place effort into designing more efficient switches 112 and 114 rather.
Yet, there still exists a need to provide an improved oscillator that eliminates the voltage overshoot or undershoot in the oscillatory signal that is not dependent upon the increased response time of the flip-flop or comparators nor dependent upon the enhanced efficiency of the switches or current sources.
To address the above-discussed deficiencies of known oscillators, the resent invention teaches an oscillator circuit having an improved capacitor discharge circuit. The first embodiment includes a first capacitor coupled to a charging circuit portion and a discharging circuit portion through a switching network. The charging circuit portion provides sufficient charge to charge the first capacitor to a high threshold voltage. The discharging circuit portion discharges the first capacitor to a low threshold voltage. The switching network alternately connects the first capacitor to the charging circuit portion and the discharging circuit portion to thereby alternately charge and discharge the first capacitor. A set/reset flip-flop is utilized to enable and disenable the charging cycle and the discharge cycle of the capacitor.
In a second embodiment, the oscillator includes a first capacitor, a first charging circuit portion, a first discharging circuit portion, and a first switching network for alternately coupling the first capacitor to the first charging circuit portion and the first discharging circuit portion. The first charging circuit portion charges the first capacitor to a high threshold voltage. The oscillator also includes a second capacitor, a second charging circuit portion and a second switching network for alternately coupling the second capacitor to the second charging circuit portion and ground such that the second capacitor charges while the first capacitor discharges and the second capacitor discharges while the first capacitor charges. The second charging circuit portion charges the second capacitor to a low threshold voltage. A set/reset flip-flop is utilized to enable and disenable the charging cycle and the discharge cycle for the first and second capacitor, alternately.
The capacitor discharge circuit in both embodiments in accordance with the present invention does not use an uncontrolled discharge current or a comparator to discharge the capacitor to a predetermined voltage. Instead, this invention uses a second capacitor charged to the opposite voltage of the first capacitor placed in parallel across the first capacitor to discharge the first capacitor. This will always discharge the first capacitor to exactly an efficient starting voltage while the third capacitor is used to facilitate the off-time.
Advantages of this design include but are not limited to a capacitor discharge circuit having a second capacitor to quickly discharge the main capacitor rather than a discharge transistor.